← CircuitGenome docs

The gm/Id Sizer — a package walkthrough

circuitgenome/sizer/gmid/ — a five-phase pipeline that turns a recognised op-amp topology and a performance spec into concrete transistor and resistor sizes.

This package sizes an analog op-amp the gm/Id way: instead of searching for widths with a solver, it computes them from a lookup table, because once the current (from KCL) and the efficiency gm/Id are fixed, the geometry follows directly. The work is split into five phases with typed hand-offs between them — like an assembly line where each station receives a labelled part and passes on a more finished one.

Each box below is clickable — it opens the intuition-first, figure-rich walkthrough for that module.

↑ Up to the full sizer overview · → See also: the shared sizing core (sizer/shared/) that both this pipeline and the Level-1 sizer are built on.

The pipeline, at a glance

The five phases, their modules, and the typed hand-offs between them. Click any box to open its walkthrough.

All pages

Design intent as a 3-level hierarchy; gm/Id inversion regions

foundation blocks.py

Functional-block view; classifies load/tail kinds

foundation analyze.py

Phase 1 — structural CircuitView, built once

phase 1 plan.py

Phases 2+3 — currents by KCL + per-device sizing plan

phase 2·3 geometry.py

Size — deterministic (W,L) forward pass, mirror ratios

phase 4 bias.py

Size — tail DC headroom repairdone

phase 4 resistors.py

Size — degeneration / tail / compensation resistors

phase 4 stage_interface.py

DC feasibility: output pin vs load window (issue #124)

phase 4 check bias_levels.py

Bias-generator level devices: cascode diodes + floors

phase 4 check evaluate.py

Phase 5 — analytical metrics, cascode-aware r_out

phase 5 gmid_sizer.py

Orchestrator — runs all five phases end-to-end

Generated by the explain-code-with-fig skill · intuition-first walkthroughs with hand-authored SVG figures · light/dark toggle top-right.