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The CircuitGenome Sizer — a full walkthrough

circuitgenome/sizer/ — Layer 3 of the pipeline: turn a recognised op-amp + a performance spec into concrete transistor and resistor sizes.

The sizer has one front door (sizer.py) that routes each circuit to one of two sizing paths — a measured gm/Id pipeline or a square-law Level-1 CP-SAT sizer — both built on a shared core. This overview mirrors the source tree; open any package to dive in, or open the dispatcher to see how the route is chosen.

The map

sizer.py · size_circuit() the dispatcher — routes by technology generic tech gm/Id LUT PTM, no LUT → error analytical/ Level-1 square-law (CP-SAT) 2 pages gmid/ gm/Id 5-phase pipeline 11 pages both build on ↓ shared/ DeviceModel · preprocess · metrics · equations · gm/Id LUT · … 9 pages One interface underneath (DeviceModel) is what lets both paths share this core.
The full sizer: one dispatcher, two sizing paths, one shared core. Click any package to open its walkthrough, or the dispatcher to see how the route is chosen.

The four packages

sizer.py
The dispatcher — routes each circuit to the right sizer, or refuses with UnsupportedTechError.
entry point · 1 page gmid/
The measured gm/Id pipeline — five phases from structural analysis to metrics.
11 pages + index analytical/
The Level-1 square-law sizer — discrete W/L via an OR-Tools CP-SAT search.
2 pages + index shared/
The model-independent core both sizers rest on, keyed on the DeviceModel interface.
9 pages + index

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