gm/Id — DC Bias (Phase 4b)

DC-bias feasibility for the gm/Id pipeline: headroom check, repair, verdict.

The gm/Id sizer assigns currents by KCL and sizes each device for a target gm/Id, but the LUT is characterized at a fixed Vds=Vdd/2 and never checks that the stacked DC operating points fit the supply with every device saturated. At low supplies (PTM nodes) this bites the tail current source: a PMOS input pair lifts its source node net_tail to Vcm + |Vgs_pair|, which can leave the PMOS tail less than its Vdsat of headroom against the rail — the tail drops into triode and sources far less than the assumed current, collapsing gm1 and GBW (issue #76, cause A).

check_dc_operating_point() runs two passes and returns (sizing, warnings, bias_feasible) without mutating its input:

  1. Headroom repair — when the tail’s Vdsat does not fit, try to lower it by raising the tail current-mirror group’s gm/Id (which keeps the mirror consistent — the same gm/Id implies the same Vgs and a width that still tracks the current ratio). When that alone cannot fit, also move the input pair toward weak inversion (raise its gm/Id → smaller |Vgs| → more tail headroom); the pair’s gm requirement is a minimum, so the stronger pair is spec-safe. If even the table’s weak-inversion limit does not fit, emit an honest warning (the SPICE DC bias-soundness check then grounds the final feasibility verdict).

  2. Cascode-aware budget — a stacked tail (cascode current source) needs the sum of the series devices’ Vdsat, which a single-device check misses (e.g. circuit_0110).

The bias_feasible verdict lets callers flag/de-rate the reported metrics when the tail can’t actually bias.

circuitgenome.sizer.gmid.bias.check_dc_operating_point(model, blocks, slot_transistors, all_transistors, ids_map, sizing, spec, tech)[source]

Return (sizing, warnings, bias_feasible).

The returned sizing reflects any tail headroom repair; the input mapping is never mutated.

Parameters:
Return type:

tuple[dict[str, TransistorSizing], list[str], bool]