gm/Id — Plan (Phases 2+3)¶

Phases 2+3 — Bias currents and the per-device sizing plan.

Phase 2 (assign_currents()) fixes what cannot be chosen: every device’s quiescent current follows from spec.ibias and KCL, and the rail-referenced load resistors follow from the first-stage branch current.

Phase 3 (plan_devices()) derives what must be achieved and what is chosen: the per-stage gm requirements and compensation caps from the performance spec (through the gm/Id device model), and the per-device design intent (role, gm/Id region, L) resolved from the functional-block registry.

Both phases are pure derivations — no geometry exists yet.

class circuitgenome.sizer.gmid.plan.CurrentPlan(ids_map, load_resistors, gd_load_r)[source]¶

Bases: object

Quiescent currents and passive loads (Phase 2 output).

Parameters:

ids_map (dict[str, float]) – ref → quiescent IDS in A, assigned from KCL + spec.ibias.
load_resistors (dict[str, float]) – ref → Ω for the rail-referenced load resistors.
gd_load_r (float) – conductance (1/R) the load resistors add at the first-stage output node; 0.0 when the load is active.

ids_map: dict[str, float]¶

load_resistors: dict[str, float]¶

gd_load_r: float¶

class circuitgenome.sizer.gmid.plan.SizingPlan(model, gm_req_map, vod_max_map, cc_pf, cc2_pf, tintents, warnings)[source]¶

Bases: object

Per-device targets and design intent (Phase 3 output).

Parameters:

model (GmIdModel) – the gm/Id device model (LUT + L/region policy from the intent).
gm_req_map (dict[str, float]) – ref → required gm in A/V (0 for non-signal devices).
vod_max_map (dict[str, float]) – ref → max VDS_sat in V from the output-swing spec (absent = unconstrained).
cc2_pf (float | None) – compensation cap(s) in pF (None when absent).
tintents (dict[str, TransistorIntent]) – ref → resolved TransistorIntent.
warnings (list[str]) – gm-ceiling advisories (a spec that needs more gm than the device can physically deliver at its bias current).
cc_pf (float | None)
cc2_pf