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The Analytical (Level-1) Sizer — a package walkthrough

circuitgenome/sizer/analytical/ — the square-law sizer that searches for discrete transistor geometry with a CP-SAT solver.

For the card-less generic technology there is no measured lookup table, so this sizer falls back on the Level-1 square law and turns sizing into a discrete search: pick integer multiples of the grid step for every W and L such that the performance requirements are met. It reuses the shared preprocessing and metric code — the only thing that differs from the gm/Id path is how geometry is chosen.

↑ Up to the full sizer overview  ·  gm/Id pipeline  ·  shared core

The pipeline — reuse shared, then solve

preprocess shared (KCL, reqs) constraints.py build CP-SAT model (linearize gm, Vdsat) CP-SAT solve discrete W, L metrics shared eval Result level1.py — the pipeline (click the frame)
Level-1 reuses the shared preprocess/metrics stations (teal); only the discrete geometry search — building & solving the CP-SAT model — is its own (accent). Click a box to open its walkthrough.

All pages

level1.py
The Level-1 pipeline — reuse shared, build/solve CP-SAT, evaluate
pipeline constraints.py
CP-SAT model builder — linearize gm≥gm_req into integer constraints
solver model

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