Index _ | A | B | C | D | E | F | G | H | I | L | M | N | O | P | Q | R | S | T | U | V | W _ _bias_diagnostic() (in module circuitgenome.sizer.shared.spice.op) _cascode_load_current_plan() (in module circuitgenome.sizer.shared.preprocess) _deck() (in module circuitgenome.sizer.shared.spice.rig) _dev_prefix() (in module circuitgenome.sizer.shared.spice.deck) _dut() (in module circuitgenome.sizer.shared.spice.deck) _edge_slew() (in module circuitgenome.sizer.shared.spice.measure) _emit_body() (in module circuitgenome.sizer.shared.spice.deck) _emit_model() (in module circuitgenome.sizer.shared.spice.deck) _evaluate_metrics() (in module circuitgenome.sizer.shared.metrics) _fb_netmap() (in module circuitgenome.sizer.shared.spice.rig) _FD_SPLIT_FRAC (in module circuitgenome.sizer.shared.spice.op) _first_stage_gain_factor() (in module circuitgenome.sizer.shared.preprocess) _inject_sizes() (in module circuitgenome.sizer.shared.spice.deck) _iref_sink() (in module circuitgenome.sizer.shared.spice.rig) _lf_mag() (in module circuitgenome.sizer.shared.spice.measure) _loop_fb() (in module circuitgenome.sizer.shared.spice.measure) _measure_ac() (in module circuitgenome.sizer.shared.spice.measure) _measure_cmrr() (in module circuitgenome.sizer.shared.spice.measure) _measure_power() (in module circuitgenome.sizer.shared.spice.measure) _measure_psrr() (in module circuitgenome.sizer.shared.spice.measure) _measure_sr() (in module circuitgenome.sizer.shared.spice.measure) _measure_swing() (in module circuitgenome.sizer.shared.spice.measure) _op_bias_problems() (in module circuitgenome.sizer.shared.spice.op) _parse_probes() (in module circuitgenome.sizer.shared.spice.op) _parse_subckt() (in module circuitgenome.sizer.shared.spice.deck) _pm_plausible() (in module circuitgenome.sizer.shared.spice.measure) _pols() (in module circuitgenome.sizer.shared.spice.measure) _read_op() (in module circuitgenome.sizer.shared.spice.op) _read_op_fd() (in module circuitgenome.sizer.shared.spice.op) _rig() (in module circuitgenome.sizer.shared.spice.rig) _run() (in module circuitgenome.sizer.shared.spice.deck) _run_capture() (in module circuitgenome.sizer.shared.spice.deck) _Topo (class in circuitgenome.sizer.shared.spice.rig) _xline() (in module circuitgenome.sizer.shared.spice.rig) _xref() (in module circuitgenome.sizer.shared.spice.deck) A accepted (circuitgenome.designer.models.TemplateStats attribute) alias_of (circuitgenome.synthesizer.models.PortDef attribute) all_transistors (circuitgenome.sizer.gmid.analyze.CircuitView attribute) analyze_circuit() (in module circuitgenome.sizer.gmid.analyze) apply_net_rename() (in module circuitgenome.synthesizer.net_aliasing) assign_currents() (in module circuitgenome.sizer.gmid.plan) assign_geometry_gmid() (in module circuitgenome.sizer.gmid.geometry) assign_ids() (in module circuitgenome.sizer.shared.preprocess) assign_slots() (in module circuitgenome.recognizer.functional_block_recognizer) B best_points (circuitgenome.designer.models.DesignReport attribute) bias_feasible (circuitgenome.sizer.shared.models.SizingResult attribute) bias_infeasible (circuitgenome.designer.models.TemplateStats attribute) (circuitgenome.synthesizer.models.ModuleVariant attribute) BiasLegLibrary (class in circuitgenome.synthesizer.models) block (circuitgenome.sizer.gmid.intent.TransistorIntent attribute) Block (class in circuitgenome.sizer.gmid.blocks) block_intents (circuitgenome.sizer.gmid.intent.GmIdIntent attribute) BlockIntent (class in circuitgenome.sizer.gmid.intent) blocks (circuitgenome.sizer.gmid.analyze.CircuitView attribute) (circuitgenome.sizer.gmid.blocks.OpAmpBlocks attribute) build_blocks() (in module circuitgenome.sizer.gmid.blocks) build_circuit() (in module circuitgenome.synthesizer.synthesizer) build_device_model() (in module circuitgenome.sizer.shared.device_model) build_model() (in module circuitgenome.sizer.analytical.constraints) C cap (circuitgenome.sizer.shared.models.TechParams attribute) CASCODE (circuitgenome.sizer.gmid.blocks.LoadKind attribute) cascode_device_refs() (in module circuitgenome.sizer.gmid.blocks) cascode_gm_id (circuitgenome.sizer.gmid.intent.GmIdIntent attribute) cascode_gmid (circuitgenome.sizer.shared.device_model.GmIdPolicy attribute) cascode_l_mult (circuitgenome.sizer.gmid.intent.GmIdIntent attribute) (circuitgenome.sizer.shared.device_model.GmIdPolicy attribute) cascode_refs (circuitgenome.sizer.gmid.analyze.CircuitView attribute) category (circuitgenome.recognizer.models.PatternDef attribute) (circuitgenome.recognizer.models.RecognizedStructure attribute) (circuitgenome.synthesizer.models.ModuleVariant attribute) (circuitgenome.synthesizer.models.Slot attribute) CategoryGroupResult (class in circuitgenome.recognizer.models) cc2_pf (circuitgenome.sizer.gmid.plan.SizingPlan attribute) (circuitgenome.sizer.shared.models.SizingResult attribute) cc_pf (circuitgenome.sizer.gmid.plan.SizingPlan attribute) (circuitgenome.sizer.shared.models.SizingResult attribute) check_bias_soundness() (in module circuitgenome.sizer.shared.spice) (in module circuitgenome.sizer.shared.spice.op) check_dc_operating_point() (in module circuitgenome.sizer.gmid.bias) check_topology_match() (in module circuitgenome.sizer.shared.preprocess) ChildDef (class in circuitgenome.recognizer.models) children (circuitgenome.recognizer.models.PatternDef attribute) (circuitgenome.recognizer.models.RecognizedStructure attribute) circuit_block (circuitgenome.recognizer.models.PatternDef attribute) (circuitgenome.recognizer.models.RecognizedStructure attribute) circuitgenome.designer.designer module circuitgenome.designer.models module circuitgenome.recognizer.functional_block_recognizer module circuitgenome.recognizer.hooks module circuitgenome.recognizer.models module circuitgenome.recognizer.netlist_parser module circuitgenome.recognizer.subcircuit_recognizer module circuitgenome.sizer.analytical.constraints module circuitgenome.sizer.analytical.level1 module circuitgenome.sizer.gmid.analyze module circuitgenome.sizer.gmid.bias module circuitgenome.sizer.gmid.bias_levels module circuitgenome.sizer.gmid.blocks module circuitgenome.sizer.gmid.evaluate module circuitgenome.sizer.gmid.geometry module circuitgenome.sizer.gmid.gmid_sizer module circuitgenome.sizer.gmid.intent module circuitgenome.sizer.gmid.plan module circuitgenome.sizer.gmid.resistors module circuitgenome.sizer.shared.device_model module circuitgenome.sizer.shared.equations module circuitgenome.sizer.shared.gmid_lut module circuitgenome.sizer.shared.loader module circuitgenome.sizer.shared.metrics module circuitgenome.sizer.shared.models module circuitgenome.sizer.shared.preprocess module circuitgenome.sizer.shared.spice module circuitgenome.sizer.shared.spice.deck module circuitgenome.sizer.shared.spice.measure module circuitgenome.sizer.shared.spice.op module circuitgenome.sizer.shared.spice.rig module circuitgenome.sizer.shared.spice.simulate module circuitgenome.sizer.shared.taxonomy module circuitgenome.sizer.sizer module circuitgenome.synthesizer.bias_construction module circuitgenome.synthesizer.compatibility.cmfb module circuitgenome.synthesizer.compatibility.compensation module circuitgenome.synthesizer.compatibility.load_branch module circuitgenome.synthesizer.compatibility.output module circuitgenome.synthesizer.compatibility.polarity module circuitgenome.synthesizer.compatibility.second_stage module circuitgenome.synthesizer.compatibility.tail_current module circuitgenome.synthesizer.loader module circuitgenome.synthesizer.models module circuitgenome.synthesizer.net_aliasing module circuitgenome.synthesizer.netlist module circuitgenome.synthesizer.synthesizer module CircuitView (class in circuitgenome.sizer.gmid.analyze) cl (circuitgenome.sizer.shared.models.SizingSpec attribute) classify_load() (in module circuitgenome.sizer.gmid.blocks) cmfb_sense_r (circuitgenome.sizer.gmid.intent.GmIdIntent attribute) cmrr_db() (in module circuitgenome.sizer.shared.equations) cmrr_min_db (circuitgenome.sizer.shared.models.SizingSpec attribute) compute_alias_net_rename() (in module circuitgenome.synthesizer.net_aliasing) compute_requirements() (in module circuitgenome.sizer.shared.preprocess) config (circuitgenome.synthesizer.models.TopologyTemplate attribute) Connection (class in circuitgenome.synthesizer.models) connections (circuitgenome.synthesizer.models.TopologyTemplate attribute) construct_bias_generation() (in module circuitgenome.synthesizer.bias_construction) constructed_bias_legs() (in module circuitgenome.recognizer.hooks) corner (circuitgenome.sizer.shared.models.SpiceLib attribute) corners (circuitgenome.sizer.shared.models.SpiceLib attribute) cs_gmid (circuitgenome.sizer.shared.device_model.GmIdPolicy attribute) cs_l_mult (circuitgenome.sizer.shared.device_model.GmIdPolicy attribute) CURRENT_SOURCE (circuitgenome.sizer.gmid.blocks.LoadKind attribute) current_source_gm_id (circuitgenome.sizer.gmid.intent.GmIdIntent attribute) current_source_l_mult (circuitgenome.sizer.gmid.intent.GmIdIntent attribute) CurrentPlan (class in circuitgenome.sizer.gmid.plan) D deduplicate_devices() (in module circuitgenome.sizer.shared.preprocess) DEFAULT_MODEL_MAP (in module circuitgenome.recognizer.netlist_parser) degeneration_factor (circuitgenome.sizer.gmid.intent.GmIdIntent attribute) design (circuitgenome.sizer.shared.models.SpiceLib attribute) design() (in module circuitgenome.designer.designer) DesignReport (class in circuitgenome.designer.models) DesignSolution (class in circuitgenome.designer.models) Device (class in circuitgenome.synthesizer.models) device_handle (circuitgenome.sizer.shared.models.TechParams attribute) device_map (circuitgenome.sizer.shared.models.TechParams attribute) DeviceModel (class in circuitgenome.sizer.shared.device_model) devices (circuitgenome.recognizer.models.ChildDef attribute) (circuitgenome.recognizer.models.ParsedNetlist attribute) (circuitgenome.recognizer.models.PatternDef attribute) (circuitgenome.recognizer.models.RecognizedStructure attribute) (circuitgenome.synthesizer.models.ModuleVariant attribute) (circuitgenome.synthesizer.models.SynthesizedCircuit attribute) diode_connected_mosfet_bias_legs() (in module circuitgenome.recognizer.hooks) display_name (circuitgenome.synthesizer.models.ModuleVariant attribute) E enumerate_circuits() (in module circuitgenome.synthesizer.synthesizer) enumerated (circuitgenome.designer.models.TemplateStats attribute) errors (circuitgenome.designer.models.TemplateStats attribute) evaluate_circuit() (in module circuitgenome.sizer.gmid.evaluate) exclusive (circuitgenome.recognizer.models.PatternDef attribute) external_ports (circuitgenome.recognizer.models.ParsedNetlist attribute) (circuitgenome.synthesizer.models.SynthesizedCircuit attribute) (circuitgenome.synthesizer.models.TopologyTemplate attribute) extra_devices (circuitgenome.recognizer.models.HookMatch attribute) extra_pins (circuitgenome.recognizer.models.HookMatch attribute) extract_slot_resistors() (in module circuitgenome.sizer.shared.preprocess) extract_slot_transistors() (in module circuitgenome.sizer.shared.preprocess) F file (circuitgenome.sizer.shared.models.SpiceLib attribute) first_stage_gain_factor() (circuitgenome.sizer.gmid.blocks.OpAmpBlocks method) first_stage_out_net() (circuitgenome.sizer.gmid.blocks.OpAmpBlocks method) ft() (circuitgenome.sizer.shared.gmid_lut.GmIdLut method) functional_block() (in module circuitgenome.sizer.gmid.intent) FunctionalBlockRecognitionResult (class in circuitgenome.recognizer.models) G gain_min_db (circuitgenome.sizer.shared.models.SizingSpec attribute) gbw_min_hz (circuitgenome.sizer.shared.models.SizingSpec attribute) gd() (in module circuitgenome.sizer.shared.equations) gd_load_r (circuitgenome.sizer.gmid.plan.CurrentPlan attribute) gd_out_extra (circuitgenome.sizer.gmid.resistors.MetricModifiers attribute) gd_tail_override (circuitgenome.sizer.gmid.resistors.MetricModifiers attribute) gds() (circuitgenome.sizer.shared.device_model.DeviceModel method) (circuitgenome.sizer.shared.device_model.GmIdModel method) (circuitgenome.sizer.shared.device_model.Level1Model method) gds_estimate() (circuitgenome.sizer.shared.device_model.DeviceModel method) (circuitgenome.sizer.shared.device_model.GmIdModel method) (circuitgenome.sizer.shared.device_model.Level1Model method) geometry_for() (circuitgenome.sizer.shared.device_model.GmIdModel method) GeomResult (class in circuitgenome.sizer.shared.device_model) gm() (circuitgenome.sizer.shared.device_model.DeviceModel method) (circuitgenome.sizer.shared.device_model.GmIdModel method) (circuitgenome.sizer.shared.device_model.Level1Model method) (in module circuitgenome.sizer.shared.equations) gm1_factor (circuitgenome.sizer.gmid.resistors.MetricModifiers attribute) gm_ceiling() (circuitgenome.sizer.shared.device_model.DeviceModel method) (circuitgenome.sizer.shared.device_model.GmIdModel method) (circuitgenome.sizer.shared.device_model.Level1Model method) (in module circuitgenome.sizer.shared.equations) gm_gds() (circuitgenome.sizer.shared.gmid_lut.GmIdLut method) gm_id (circuitgenome.sizer.gmid.intent.BlockIntent attribute) (circuitgenome.sizer.gmid.intent.TransistorIntent attribute) (circuitgenome.sizer.shared.device_model.GeomResult attribute) gm_id_capped (circuitgenome.sizer.shared.device_model.GeomResult attribute) gm_id_from_idw() (circuitgenome.sizer.shared.gmid_lut.GmIdLut method) gm_req_map (circuitgenome.sizer.gmid.plan.SizingPlan attribute) gmid_lut (circuitgenome.sizer.shared.models.TechParams attribute) GmIdIntent (class in circuitgenome.sizer.gmid.intent) GmIdLut (class in circuitgenome.sizer.shared.gmid_lut) GmIdModel (class in circuitgenome.sizer.shared.device_model) GmIdPolicy (class in circuitgenome.sizer.shared.device_model) GridSpec (class in circuitgenome.sizer.shared.models) group_by_category() (in module circuitgenome.recognizer.functional_block_recognizer) groups (circuitgenome.recognizer.models.CategoryGroupResult attribute) H has_cascode_load() (circuitgenome.sizer.gmid.blocks.OpAmpBlocks method) has_cascode_tail() (circuitgenome.sizer.gmid.blocks.OpAmpBlocks method) hook (circuitgenome.recognizer.models.PatternDef attribute) HookMatch (class in circuitgenome.recognizer.models) I ibias (circuitgenome.sizer.shared.models.SizingSpec attribute) id_per_w() (circuitgenome.sizer.shared.gmid_lut.GmIdLut method) ids_a (circuitgenome.sizer.shared.models.TransistorSizing attribute) ids_map (circuitgenome.sizer.gmid.plan.CurrentPlan attribute) index (circuitgenome.recognizer.models.RecognizedStructure attribute) input_pair (circuitgenome.sizer.gmid.blocks.OpAmpBlocks property) internal_nets (circuitgenome.recognizer.models.ParsedNetlist attribute) is_cascode (circuitgenome.sizer.gmid.blocks.Block property) is_cmfb_compatible() (in module circuitgenome.synthesizer.compatibility.cmfb) is_combination_valid() (in module circuitgenome.synthesizer.compatibility.polarity) is_compensation_compatible() (in module circuitgenome.synthesizer.compatibility.compensation) is_fully_differential (circuitgenome.sizer.gmid.blocks.OpAmpBlocks attribute) is_gmid (circuitgenome.sizer.shared.device_model.DeviceModel attribute) (circuitgenome.sizer.shared.device_model.GmIdModel attribute) (circuitgenome.sizer.shared.device_model.Level1Model attribute) is_load_branch_compatible() (in module circuitgenome.synthesizer.compatibility.load_branch) is_output_type_compatible() (in module circuitgenome.synthesizer.compatibility.output) is_second_stage_compatible() (in module circuitgenome.synthesizer.compatibility.second_stage) is_signal_device() (in module circuitgenome.sizer.shared.taxonomy) is_tail_current_compatible() (in module circuitgenome.synthesizer.compatibility.tail_current) L l_mult (circuitgenome.sizer.gmid.intent.BlockIntent attribute) (circuitgenome.sizer.gmid.intent.TransistorIntent attribute) l_um (circuitgenome.sizer.shared.device_model.GeomResult attribute) (circuitgenome.sizer.shared.models.TransistorSizing attribute) lam (circuitgenome.sizer.shared.models.MosfetParams attribute) legs (circuitgenome.synthesizer.models.BiasLegLibrary attribute) length (circuitgenome.sizer.shared.models.TechParams attribute) length_for() (circuitgenome.sizer.shared.device_model.GmIdModel method) Level1Model (class in circuitgenome.sizer.shared.device_model) load (circuitgenome.sizer.gmid.blocks.OpAmpBlocks property) load_bias_legs() (in module circuitgenome.synthesizer.loader) load_kind (circuitgenome.sizer.gmid.blocks.Block attribute) load_modules() (in module circuitgenome.synthesizer.loader) load_patterns() (in module circuitgenome.recognizer.subcircuit_recognizer) load_resistors (circuitgenome.sizer.gmid.plan.CurrentPlan attribute) load_spec() (in module circuitgenome.sizer.shared.loader) load_tech() (in module circuitgenome.sizer.shared.loader) load_topologies() (in module circuitgenome.synthesizer.loader) LoadKind (class in circuitgenome.sizer.gmid.blocks) M magic_battery_bias_legs() (in module circuitgenome.recognizer.hooks) margins (circuitgenome.designer.models.DesignSolution attribute) (circuitgenome.sizer.shared.models.SizingResult attribute) max (circuitgenome.sizer.shared.models.GridSpec attribute) max_gm_id() (circuitgenome.sizer.shared.gmid_lut.GmIdLut method) MetricModifiers (class in circuitgenome.sizer.gmid.resistors) metrics (circuitgenome.designer.models.DesignSolution attribute) (circuitgenome.sizer.shared.models.SizingResult attribute) min (circuitgenome.sizer.shared.models.GridSpec attribute) MIRROR (circuitgenome.sizer.gmid.blocks.LoadKind attribute) model (circuitgenome.sizer.gmid.plan.SizingPlan attribute) module circuitgenome.designer.designer circuitgenome.designer.models circuitgenome.recognizer.functional_block_recognizer circuitgenome.recognizer.hooks circuitgenome.recognizer.models circuitgenome.recognizer.netlist_parser circuitgenome.recognizer.subcircuit_recognizer circuitgenome.sizer.analytical.constraints circuitgenome.sizer.analytical.level1 circuitgenome.sizer.gmid.analyze circuitgenome.sizer.gmid.bias circuitgenome.sizer.gmid.bias_levels circuitgenome.sizer.gmid.blocks circuitgenome.sizer.gmid.evaluate circuitgenome.sizer.gmid.geometry circuitgenome.sizer.gmid.gmid_sizer circuitgenome.sizer.gmid.intent circuitgenome.sizer.gmid.plan circuitgenome.sizer.gmid.resistors circuitgenome.sizer.shared.device_model circuitgenome.sizer.shared.equations circuitgenome.sizer.shared.gmid_lut circuitgenome.sizer.shared.loader circuitgenome.sizer.shared.metrics circuitgenome.sizer.shared.models circuitgenome.sizer.shared.preprocess circuitgenome.sizer.shared.spice circuitgenome.sizer.shared.spice.deck circuitgenome.sizer.shared.spice.measure circuitgenome.sizer.shared.spice.op circuitgenome.sizer.shared.spice.rig circuitgenome.sizer.shared.spice.simulate circuitgenome.sizer.shared.taxonomy circuitgenome.sizer.sizer circuitgenome.synthesizer.bias_construction circuitgenome.synthesizer.compatibility.cmfb circuitgenome.synthesizer.compatibility.compensation circuitgenome.synthesizer.compatibility.load_branch circuitgenome.synthesizer.compatibility.output circuitgenome.synthesizer.compatibility.polarity circuitgenome.synthesizer.compatibility.second_stage circuitgenome.synthesizer.compatibility.tail_current circuitgenome.synthesizer.loader circuitgenome.synthesizer.models circuitgenome.synthesizer.net_aliasing circuitgenome.synthesizer.netlist circuitgenome.synthesizer.synthesizer ModuleVariant (class in circuitgenome.synthesizer.models) MosfetParams (class in circuitgenome.sizer.shared.models) mosfets (circuitgenome.sizer.gmid.blocks.Block attribute) mu_cox (circuitgenome.sizer.shared.models.MosfetParams attribute) N n_stages (circuitgenome.sizer.gmid.blocks.OpAmpBlocks attribute) name (circuitgenome.designer.models.DesignSolution attribute) (circuitgenome.recognizer.models.ParsedNetlist attribute) (circuitgenome.recognizer.models.PatternDef attribute) (circuitgenome.recognizer.models.RecognizedStructure attribute) (circuitgenome.sizer.gmid.blocks.Block attribute) (circuitgenome.sizer.shared.models.TechParams attribute) (circuitgenome.synthesizer.models.ModuleVariant attribute) (circuitgenome.synthesizer.models.PortDef attribute) (circuitgenome.synthesizer.models.Slot attribute) (circuitgenome.synthesizer.models.SynthesizedCircuit attribute) (circuitgenome.synthesizer.models.TopologyTemplate attribute) net (circuitgenome.synthesizer.models.Connection attribute) netlist_path (circuitgenome.designer.models.DesignSolution attribute) ngspice_available() (in module circuitgenome.sizer.shared.spice) (in module circuitgenome.sizer.shared.spice.deck) nmos (circuitgenome.sizer.shared.models.TechParams attribute) node_rout() (in module circuitgenome.sizer.gmid.blocks) NONE (circuitgenome.sizer.gmid.blocks.LoadKind attribute) notes (circuitgenome.designer.models.DesignSolution attribute) O OpAmpBlocks (class in circuitgenome.sizer.gmid.blocks) open_loop_gain_db() (in module circuitgenome.sizer.shared.equations) orient_cmfb() (in module circuitgenome.synthesizer.compatibility.cmfb) output_cardinality (circuitgenome.synthesizer.models.ModuleVariant attribute) output_swing_max_v (circuitgenome.sizer.shared.models.SizingSpec attribute) output_swing_min_v (circuitgenome.sizer.shared.models.SizingSpec attribute) P params (circuitgenome.synthesizer.models.Device attribute) parse() (in module circuitgenome.recognizer.netlist_parser) ParsedNetlist (class in circuitgenome.recognizer.models) pattern (circuitgenome.recognizer.models.ChildDef attribute) pattern_name (circuitgenome.recognizer.models.SlotAssignment attribute) PatternDef (class in circuitgenome.recognizer.models) PatternDevice (class in circuitgenome.recognizer.models) pdk_netlist() (in module circuitgenome.sizer.shared.spice) (in module circuitgenome.sizer.shared.spice.deck) phase_margin_min_deg (circuitgenome.sizer.shared.models.SizingSpec attribute) phase_margin_three_stage_deg() (in module circuitgenome.sizer.shared.equations) phase_margin_two_stage_deg() (in module circuitgenome.sizer.shared.equations) pins (circuitgenome.recognizer.models.PatternDef attribute) (circuitgenome.recognizer.models.RecognizedStructure attribute) plan_devices() (in module circuitgenome.sizer.gmid.plan) pmos (circuitgenome.sizer.shared.models.TechParams attribute) polarity (circuitgenome.synthesizer.models.ModuleVariant attribute) port (circuitgenome.synthesizer.models.Connection attribute) port_names() (circuitgenome.synthesizer.models.ModuleVariant method) PortDef (class in circuitgenome.synthesizer.models) ports (circuitgenome.synthesizer.models.ModuleVariant attribute) power_max_w (circuitgenome.sizer.shared.models.SizingSpec attribute) pref_branch (circuitgenome.synthesizer.models.BiasLegLibrary attribute) PREF_KINDS (in module circuitgenome.synthesizer.bias_construction) priority (circuitgenome.recognizer.models.PatternDef attribute) prune_cmfb() (in module circuitgenome.synthesizer.compatibility.cmfb) prune_tail_current() (in module circuitgenome.synthesizer.compatibility.tail_current) psrr_db_approx() (in module circuitgenome.sizer.shared.equations) psrr_min_db (circuitgenome.sizer.shared.models.SizingSpec attribute) Q quiescent_power() (in module circuitgenome.sizer.shared.equations) R rail_flavor_from_diode() (in module circuitgenome.synthesizer.bias_construction) rationale (circuitgenome.sizer.gmid.intent.BlockIntent attribute) (circuitgenome.sizer.gmid.intent.TransistorIntent attribute) read_op_operating_point() (in module circuitgenome.sizer.shared.spice) (in module circuitgenome.sizer.shared.spice.op) recognize() (in module circuitgenome.recognizer.subcircuit_recognizer) RecognizedStructure (class in circuitgenome.recognizer.models) ref (circuitgenome.recognizer.models.PatternDevice attribute) (circuitgenome.sizer.gmid.intent.TransistorIntent attribute) (circuitgenome.sizer.shared.models.TransistorSizing attribute) (circuitgenome.synthesizer.models.Device attribute) reference (circuitgenome.synthesizer.models.BiasLegLibrary attribute) rejection_reasons (circuitgenome.designer.models.TemplateStats attribute) required_pair_type() (in module circuitgenome.synthesizer.compatibility.second_stage) required_rail_kinds() (in module circuitgenome.synthesizer.bias_construction) RESISTOR (circuitgenome.sizer.gmid.blocks.LoadKind attribute) resistor_bias_legs() (in module circuitgenome.recognizer.hooks) resistor_load_gnd_check() (in module circuitgenome.recognizer.hooks) resistor_load_vdd_check() (in module circuitgenome.recognizer.hooks) resistor_tail_gnd_check() (in module circuitgenome.recognizer.hooks) resistor_tail_vdd_check() (in module circuitgenome.recognizer.hooks) resistors (circuitgenome.sizer.gmid.blocks.Block attribute) (circuitgenome.sizer.shared.models.SizingResult attribute) resolve_transistor_intents() (in module circuitgenome.sizer.gmid.intent) role (circuitgenome.sizer.gmid.intent.BlockIntent attribute) (circuitgenome.sizer.gmid.intent.TransistorIntent attribute) (circuitgenome.synthesizer.models.PortDef attribute) role_length() (circuitgenome.sizer.shared.device_model.GmIdModel method) rout() (in module circuitgenome.sizer.shared.equations) runtime_s (circuitgenome.designer.models.DesignReport attribute) (circuitgenome.designer.models.TemplateStats attribute) S same_net (circuitgenome.recognizer.models.PatternDef attribute) second_stage_current_ratio (circuitgenome.sizer.shared.models.SizingSpec attribute) signal_device (circuitgenome.sizer.gmid.blocks.Block property) signal_device_type() (in module circuitgenome.synthesizer.compatibility.second_stage) signal_gm_id (circuitgenome.sizer.gmid.intent.GmIdIntent attribute) signal_l_mult (circuitgenome.sizer.gmid.intent.GmIdIntent attribute) (circuitgenome.sizer.shared.device_model.GmIdPolicy attribute) signal_nominal_gmid (circuitgenome.sizer.shared.device_model.GmIdPolicy attribute) simulate_metrics() (in module circuitgenome.sizer.shared.spice) (in module circuitgenome.sizer.shared.spice.simulate) size_circuit() (in module circuitgenome.sizer.sizer) size_gmid() (in module circuitgenome.sizer.gmid.gmid_sizer) size_level1() (in module circuitgenome.sizer.analytical.level1) size_load_resistors() (in module circuitgenome.sizer.shared.preprocess) size_resistors() (in module circuitgenome.sizer.gmid.resistors) sized_netlist() (in module circuitgenome.sizer.shared.spice) (in module circuitgenome.sizer.shared.spice.deck) sizing_failed (circuitgenome.designer.models.TemplateStats attribute) SizingPlan (class in circuitgenome.sizer.gmid.plan) SizingResult (class in circuitgenome.sizer.shared.models) SizingSpec (class in circuitgenome.sizer.shared.models) slew_rate_min_vps (circuitgenome.sizer.shared.models.SizingSpec attribute) slew_rate_vps() (in module circuitgenome.sizer.shared.equations) slot (circuitgenome.synthesizer.models.Connection attribute) Slot (class in circuitgenome.synthesizer.models) slot_assignments (circuitgenome.recognizer.models.FunctionalBlockRecognitionResult attribute) slot_connections() (circuitgenome.synthesizer.models.TopologyTemplate method) slot_name (circuitgenome.recognizer.models.SlotAssignment attribute) slot_resistors (circuitgenome.sizer.gmid.analyze.CircuitView attribute) slot_transistors (circuitgenome.sizer.gmid.analyze.CircuitView attribute) SlotAssignment (class in circuitgenome.recognizer.models) slots (circuitgenome.synthesizer.models.TopologyTemplate attribute) solutions (circuitgenome.designer.models.DesignReport attribute) solver_status (circuitgenome.sizer.shared.models.SizingResult attribute) spec (circuitgenome.designer.models.DesignReport attribute) spec_failed (circuitgenome.designer.models.TemplateStats attribute) spice_lib (circuitgenome.sizer.shared.models.TechParams attribute) spice_model (circuitgenome.sizer.shared.models.TechParams attribute) SpiceLib (class in circuitgenome.sizer.shared.models) stage_inversions() (in module circuitgenome.synthesizer.compatibility.compensation) stats (circuitgenome.designer.models.DesignReport attribute) step (circuitgenome.sizer.shared.models.GridSpec attribute) structure (circuitgenome.recognizer.models.SlotAssignment attribute) structures (circuitgenome.recognizer.models.SubcircuitRecognitionResult attribute) SubcircuitRecognitionResult (class in circuitgenome.recognizer.models) swing_gm_id_floor() (in module circuitgenome.sizer.gmid.geometry) synthesize() (in module circuitgenome.synthesizer.synthesizer) SynthesizedCircuit (class in circuitgenome.synthesizer.models) T tail (circuitgenome.sizer.gmid.blocks.OpAmpBlocks property) tail_net() (circuitgenome.sizer.gmid.blocks.OpAmpBlocks method) tech (circuitgenome.designer.models.DesignReport attribute) tech_type (circuitgenome.recognizer.models.RecognizedStructure attribute) tech_type_from (circuitgenome.recognizer.models.PatternDef attribute) TechParams (class in circuitgenome.sizer.shared.models) template (circuitgenome.designer.models.TemplateStats attribute) TemplateStats (class in circuitgenome.designer.models) terminals (circuitgenome.synthesizer.models.Device attribute) third_stage_current_ratio (circuitgenome.sizer.shared.models.SizingSpec attribute) tintents (circuitgenome.sizer.gmid.plan.SizingPlan attribute) to_flat_spice() (in module circuitgenome.synthesizer.netlist) to_hierarchical_spice() (in module circuitgenome.synthesizer.netlist) topology (circuitgenome.designer.models.DesignSolution attribute) (circuitgenome.synthesizer.models.SynthesizedCircuit attribute) TopologyTemplate (class in circuitgenome.synthesizer.models) transistor_intents (circuitgenome.sizer.shared.models.SizingResult attribute) TransistorIntent (class in circuitgenome.sizer.gmid.intent) transistors (circuitgenome.sizer.shared.models.SizingResult attribute) TransistorSizing (class in circuitgenome.sizer.shared.models) tune_bias_levels() (in module circuitgenome.sizer.gmid.bias_levels) type (circuitgenome.recognizer.models.PatternDevice attribute) (circuitgenome.synthesizer.models.Device attribute) U unassigned_structures (circuitgenome.recognizer.models.FunctionalBlockRecognitionResult attribute) unity_gain_bw() (in module circuitgenome.sizer.shared.equations) unrecognized_devices (circuitgenome.recognizer.models.CategoryGroupResult attribute) (circuitgenome.recognizer.models.FunctionalBlockRecognitionResult attribute) (circuitgenome.recognizer.models.SubcircuitRecognitionResult attribute) unsized_mos_refs() (in module circuitgenome.sizer.shared.spice.deck) unsupported (circuitgenome.synthesizer.models.ModuleVariant attribute) UnsupportedTechError untapped_branch_is_dc_defined() (in module circuitgenome.synthesizer.compatibility.load_branch) unverified (circuitgenome.designer.models.TemplateStats attribute) unverified_specs (circuitgenome.designer.models.DesignReport attribute) V variant_map (circuitgenome.synthesizer.models.SynthesizedCircuit attribute) variants (circuitgenome.designer.models.DesignSolution attribute) vdd (circuitgenome.sizer.shared.models.SizingSpec attribute) vds_sat() (circuitgenome.sizer.shared.device_model.DeviceModel method) (circuitgenome.sizer.shared.device_model.GmIdModel method) (circuitgenome.sizer.shared.device_model.Level1Model method) (in module circuitgenome.sizer.shared.equations) vds_sat_v (circuitgenome.sizer.shared.models.TransistorSizing attribute) vdsat() (circuitgenome.sizer.shared.gmid_lut.GmIdLut method) vgs() (circuitgenome.sizer.shared.device_model.DeviceModel method) (circuitgenome.sizer.shared.device_model.GmIdModel method) (circuitgenome.sizer.shared.device_model.Level1Model method) (circuitgenome.sizer.shared.gmid_lut.GmIdLut method) vgs_from_ids() (in module circuitgenome.sizer.shared.equations) vgs_v (circuitgenome.sizer.shared.models.TransistorSizing attribute) vod_max_map (circuitgenome.sizer.gmid.plan.SizingPlan attribute) vss (circuitgenome.sizer.shared.models.SizingSpec attribute) vth (circuitgenome.sizer.shared.models.MosfetParams attribute) W w_um (circuitgenome.sizer.shared.device_model.GeomResult attribute) (circuitgenome.sizer.shared.models.TransistorSizing attribute) warnings (circuitgenome.sizer.gmid.analyze.CircuitView attribute) (circuitgenome.sizer.gmid.plan.SizingPlan attribute) (circuitgenome.sizer.shared.models.SizingResult attribute) width (circuitgenome.sizer.shared.models.TechParams attribute) wl_units (circuitgenome.sizer.shared.models.TechParams attribute) worst_margin (circuitgenome.designer.models.DesignSolution attribute)