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CircuitGenome
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CircuitGenome

Getting Started

  • Installation
  • Overview

User Guide

  • CLI Usage
  • Python API

Modules

  • Topology Synthesizer
    • Compatibility Filters
      • Polarity Compatibility
      • Stage-Interface Compatibility
      • Compensation Compatibility
      • Output Compatibility
      • Load Branch Compatibility
      • CMFB Compatibility
      • Tail-Current Compatibility
    • Synthesizer
    • Models
    • Loader
    • Netlist
    • Bias Construction
    • Net Aliasing
  • Subcircuit Recognizer
    • Netlist Parser
    • Subcircuit Recognizer
    • Hooks
    • Models
  • Functional Block Recognizer
    • Functional Block Recognizer
  • Sizer
    • Theory
      • Analytical Sizing Flow
      • gm/Id Sizing Flow
    • Shared API
      • Sizer
      • Models
      • Loader
      • Device Model
      • Equations
      • gm/Id LUT
      • SPICE Verification
      • Template Taxonomy
      • Preprocessing
      • Metric Evaluation
    • Analytical Sizer
      • Level-1 Sizer
      • Constraints
    • gm/Id Sizer
      • gm/Id — Gmid Sizer
      • gm/Id — Analyze (Phase 1)
      • gm/Id — Plan (Phases 2+3)
      • gm/Id — DC Bias (Phase 4b)
      • gm/Id — Evaluate (Phase 5)
      • gm/Id — Blocks
      • gm/Id — Intent
      • gm/Id — Geometry
      • gm/Id — Resistors
      • gm/Id — Bias Levels
  • Designer
    • Designer
    • Designer — Models
  • Visualizer

Walkthroughs

  • Code Walkthroughs

About

  • Extending CircuitGenome
  • Contributing
  • References
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