Designer

Designer module (Layer 4): synthesize → size → SPICE-verify → export.

design() closes the loop the other layers leave manual: enumerate every valid circuit for the chosen template(s) (synthesizer), size each with the gm/Id sizer (recognizer + sizer), keep the circuits whose ngspice-measured metrics meet the target spec, export the survivors as sized flat SPICE netlists, and report statistics with the best design points.

Acceptance is strict: a circuit is rejected when its sizing fails, its DC bias is infeasible (analytical or SPICE-grounded), the sizer’s own gain estimate falls more than _ANALYTIC_GAIN_TOL_DB below gain_min_db (issue #125 — the SPICE bench is skipped for these), any measured spec is missed, or a constrained spec could not be SPICE-measured (stage unverified — this includes structurally unmeasurable cases such as swing/slew on fully-differential topologies). The affected spec fields are surfaced in the report’s unverified_specs, and every rejection’s detail is histogrammed in each template’s rejection_reasons.

circuitgenome.designer.designer.design(spec, output_dir, templates=None, tech='gf180mcu', limit=None, workers=1, include_infeasible=False, progress=None)[source]

Synthesize, size and SPICE-verify circuits against spec; export the designs that meet it.

Parameters:

  • spec (SizingSpec | str | Path) – the target SizingSpec, or a path to its YAML file.

  • output_dir (str | Path) – where the sized netlists (one <topology>/ folder per template) and report.json are written. Created if missing.

  • templates (Iterable[str] | None) – topology template names to design, or None for all.

  • tech (TechParams | str | Path) – technology (TechParams, built-in name or YAML path). Must carry a gm/Id LUT — this pipeline sizes with the gm/Id sizer.

  • limit (int | None) – evaluate at most this many circuits per template (enumeration order); None = exhaustive.

  • workers (int) – parallel worker processes for size+simulate (1 = in-process).

  • include_infeasible (bool) – when True, also evaluate variants tagged bias_infeasible (functionally-correct wiring the default spec class cannot bias, e.g. the stacked-diode cascode tails, issue #111). For design-space exploration; these are expected to be rejected at the DC bias gate (the "bias_infeasible" outcome).

  • progress (Callable[[str], None] | None) – optional line sink (e.g. print) for progress output.

Returns:

the DesignReport (also written as report.json).

Raises:

  • RuntimeError – when ngspice is not on PATH (acceptance is SPICE-measured by definition).

  • ValueError – for an unknown template name or a tech without a gm/Id LUT.

Return type:

DesignReport