Constraints¶
OR-Tools CP-SAT model builder for transistor sizing.
Translates performance requirements into integer linear constraints over discrete W and L variables (in integer multiples of the grid step).
Key linearisation: the gm lower-bound constraint
gm ≥ gm_req ↔ √(2·µCox·(W/L)·IDS) ≥ gm_req ↔ 2·µCox·IDS·W ≥ gm_req²·L [linear in W, L]
and the VDS_sat upper-bound constraint
√(2·IDS·L/(µCox·W)) ≤ VDS_sat_max ↔ 2·IDS·L ≤ µCox·VDS_sat_max²·W [linear in W, L]
are both linear once W and L are separate integer variables. The integer variables count grid steps (W_µm = W·width.step), so each side’s step size is folded into its coefficient. All floating-point coefficients are scaled by _SCALE = 10¹² before rounding to integers so that µA/V² and µA magnitudes map to small integer values.
- circuitgenome.sizer.analytical.constraints.build_model(transistors, slot_transistors, ids_map, gm_req_map, vod_max_map, tech, symmetry_slots=frozenset({'input_pair', 'load', 'tail_current'}))[source]¶
Build the CP-SAT sizing model.
- Parameters:
transistors (dict[str, tuple]) – Deduplicated map of all transistors to size, keyed by device reference.
slot_transistors (dict[str, list]) – Per-slot transistor lists (for symmetry grouping).
ids_map (dict[str, float]) – Quiescent drain-source current in A for each transistor.
gm_req_map (dict[str, float]) – Required transconductance lower bound in A/V. Entries with value ≤ 0 are skipped.
vod_max_map (dict[str, float]) – Maximum VDS_sat (overdrive) in V. Entries with value ≥ a large number are skipped.
tech (TechParams) – Technology parameters supplying µCox, Vth, λ and grids.
symmetry_slots (frozenset[str]) – Slot names within which same-type transistors are constrained to equal W and equal L (matched pairs).
- Returns:
(model, W_vars, L_vars)whereW_varsandL_varsare dicts mapping device reference to the correspondingcp_model.IntVar(in integer grid steps, not µm).- Return type: