Designer — Models

Data models for the Designer module (Layer 4).

Plain dataclasses — they carry no logic and serialize straight into the report.json the designer writes next to the exported netlists.

class circuitgenome.designer.models.DesignSolution(name, topology, variants, metrics, margins, worst_margin, netlist_path, notes=<factory>)[source]

Bases: object

One accepted design: a synthesized circuit whose sized, SPICE-measured performance meets every measurable spec.

Parameters:

  • name (str) – enumeration name (circuit_0007), matching the index the synthesizer CLI would assign, so solutions cross-reference cg synthesize output.

  • topology (str) – the TopologyTemplate name.

  • variants (dict[str, str]) – slot name → chosen module-variant name.

  • metrics (dict[str, float | None]) – ngspice-measured metrics (gain_db, gbw_hz, phase_margin_deg, slew_rate_vps, power_w, cmrr_db, psrr_db, output_swing_max_v, output_swing_min_v); None when a measurement could not be extracted.

  • margins (dict[str, float]) – normalized margin per constrained+measured spec ((meas − min)/min for min-specs, (max − meas)/max for max-specs); every value is ≥ 0 by construction.

  • worst_margin (float) – the smallest margin (inf when no measured spec constrains this design) — the robustness ranking key.

  • netlist_path (str) – the sized flat SPICE netlist written for this design.

  • notes (list[str]) – advisory lines from the measurement rig (e.g. why an unconstrained metric could not be extracted).

name: str
topology: str
variants: dict[str, str]
metrics: dict[str, float | None]
margins: dict[str, float]
worst_margin: float
netlist_path: str
notes: list[str]
class circuitgenome.designer.models.TemplateStats(template, enumerated=0, sizing_failed=0, bias_infeasible=0, spec_failed=0, unverified=0, errors=0, accepted=0, runtime_s=0.0, rejection_reasons=<factory>)[source]

Bases: object

Counts for one template’s enumerate→size→verify run.

enumerated counts the candidates actually evaluated (after limit); the rejection counters partition enumerated − accepted by the pipeline stage that rejected the circuit. rejection_reasons histograms the per-candidate rejection details (numerals collapsed to # so identical failure classes aggregate), ordered most-common first.

Parameters:
template: str
enumerated: int = 0
sizing_failed: int = 0
bias_infeasible: int = 0
spec_failed: int = 0
unverified: int = 0
errors: int = 0
accepted: int = 0
runtime_s: float = 0.0
rejection_reasons: dict[str, int]
class circuitgenome.designer.models.DesignReport(spec, tech, solutions=<factory>, stats=<factory>, best_points=<factory>, unverified_specs=<factory>, runtime_s=0.0)[source]

Bases: object

Output of design().

Parameters:

  • spec (dict) – echo of the target SizingSpec fields.

  • tech (str) – technology name the run sized and simulated against.

  • solutions (list[DesignSolution]) – every accepted design, in enumeration order.

  • stats (dict[str, TemplateStats]) – per-template counters, keyed by topology name.

  • best_points (dict[str, DesignSolution]) – criterion → the winning solution among solutions (highest_gain, highest_gbw, highest_phase_margin, lowest_power, most_robust).

  • unverified_specs (list[str]) – constrained spec fields whose measurement came back None for at least one candidate (e.g. swing/slew on fully-differential topologies) — such candidates are rejected as unverified; acceptance requires every constrained spec to be SPICE-measured and met.

  • runtime_s (float) – wall-clock time for the whole run.

spec: dict
tech: str
solutions: list[DesignSolution]
stats: dict[str, TemplateStats]
best_points: dict[str, DesignSolution]
unverified_specs: list[str]
runtime_s: float = 0.0