gm/Id — Gmid Sizer

Orchestrator for the block-based gm/Id sizing pipeline.

size_gmid runs the gm/Id path end-to-end, separate from the Level-1 CP-SAT sizer, as five phases with explicit hand-offs:

  1. Analyze (analyze) — structural view: slots, blocks, cascodes, topology-mismatch warnings → CircuitView.

  2. Bias currents (plan) — per-device IDS from KCL + spec.ibias and the rail-referenced load resistors → CurrentPlan.

  3. Plan (plan) — per-stage gm requirements and compensation caps from the spec, per-device design intent from the functional-block registry → SizingPlan.

  4. Size — deterministic geometry from the LUT (geometry), the DC operating-point check and tail repair (bias), the stage-interface window check and repair (stage_interface), the non-load resistor network (resistors), and the constructed-bias level tuning (bias_levels).

  5. Evaluate (evaluate) — cascode-aware analytical metrics.

The model-independent topology math is reused from the circuitgenome.sizer.shared package rather than duplicated.

circuitgenome.sizer.gmid.gmid_sizer.size_gmid(parsed, sr_result, fbr_result, topology, tech, spec, intent=GmIdIntent(block_intents={'input_stage': BlockIntent(role='signal', gm_id=None, l_mult=2.0, rationale='Convert the differential input voltage to current with high gm, low noise and good matching. gm/Id is solved to meet GBW/gain (moderate inversion); a small L multiple balances gain and ft.'), 'gain_stage': BlockIntent(role='signal', gm_id=None, l_mult=2.0, rationale='Increase voltage gain while maintaining stability. gm/Id is solved from the required gm; L favours a gain/ft balance.'), 'output_stage': BlockIntent(role='signal', gm_id=None, l_mult=2.0, rationale='Drive the load capacitance and provide slew current. gm/Id is solved from the required gm.'), 'active_load': BlockIntent(role='current_source', gm_id=10.0, l_mult=4.0, rationale='First-stage active current-mirror load: replicate current accurately with high output resistance. Strong-ish inversion (low gm/Id) for headroom and rout; a long L raises rout.'), 'stage_load': BlockIntent(role='current_source', gm_id=10.0, l_mult=4.0, rationale='Current-source load of a gain/output stage: high output resistance for gain. Strong-ish inversion, long L.'), 'tail_current': BlockIntent(role='current_source', gm_id=10.0, l_mult=4.0, rationale='Tail current source: set the input-pair bias current with adequate saturation headroom and high rout. A low gm/Id (strong inversion) maximises the headroom.'), 'bias_generator': BlockIntent(role='current_source', gm_id=10.0, l_mult=4.0, rationale='Generate stable, low-sensitivity reference currents for the mirrors it drives. Strong inversion, long L to match those mirrors.'), 'cmfb': BlockIntent(role='current_source', gm_id=10.0, l_mult=4.0, rationale='Common-mode feedback devices: regulate the output common-mode voltage. (Resistive-sense averaging is set separately by cmfb_sense_r.)'), 'cascode': BlockIntent(role='cascode', gm_id=8.0, l_mult=3.0, rationale='Increase output resistance while preserving the stacked headroom. Strong inversion for a small Vdsat; a moderate L.'), 'current_source': BlockIntent(role='current_source', gm_id=10.0, l_mult=4.0, rationale='Generic current source: accurate current with high output resistance. Strong-ish inversion, long L.')}, signal_gm_id=14.0, current_source_gm_id=10.0, cascode_gm_id=8.0, signal_l_mult=2.0, current_source_l_mult=4.0, cascode_l_mult=3.0, degeneration_factor=0.5, cmfb_sense_r=1000000.0))[source]

Size a circuit via the gm/Id pipeline. Requires tech.gmid_lut.

Parameters:
Return type:

SizingResult