Sizer

Initial Sizing module — Layer 3 of the CircuitGenome pipeline.

size_circuit() is the dispatcher: it routes a parsed netlist plus its Layer-2 FunctionalBlockRecognitionResult and a performance spec to the right sizer and returns a SizingResult.

• technologies with a gm/Id LUT → the block-based gm/Id pipeline (size_gmid());

• the card-less generic technology → the Level-1 CP-SAT sizer (size_level1());

• a PTM/SPICE-model node without a LUT → UnsupportedTechError (the Level-1 square-law numbers are not valid for such nodes).

circuitgenome.sizer.sizer.size_circuit(parsed, sr_result, fbr_result, topology, tech, spec, *, time_limit_s=30.0)

Compute initial transistor W/L values satisfying spec.

Parameters:

• parsed (ParsedNetlist) – Layer-0 parsed netlist.

• sr_result (SubcircuitRecognitionResult) – Layer-1 subcircuit recognition result (unused directly but kept for API symmetry with the pipeline).

• fbr_result (FunctionalBlockRecognitionResult) – Layer-2 FBR result from assign_slots(). Must use topology mode (not group-by-category).

• topology (TopologyTemplate) – Topology template corresponding to fbr_result.

• tech (TechParams) – Technology parameters (from load_tech()).

• spec (SizingSpec) – Performance specification.

• time_limit_s (float) – CP-SAT solver time limit in seconds (Level-1 path only).

Returns:

SizingResult with per-transistor sizing, compensation cap, computed metrics, and safety margins.

Return type:

SizingResult