Level-1 Sizer¶
Level-1 (square-law) sizing pipeline: discrete W/L via OR-Tools CP-SAT.
Used for the card-less generic technology. Reuses the shared preprocessing
(circuitgenome.sizer.shared.preprocess) and metric evaluation
(circuitgenome.sizer.shared.metrics); the discrete geometry search is built
in constraints.
- circuitgenome.sizer.analytical.level1.size_level1(parsed, sr_result, fbr_result, topology, tech, spec, *, time_limit_s=30.0)[source]¶
Size a circuit with the Level-1 square-law model + CP-SAT geometry search.
- Parameters:
parsed (ParsedNetlist)
sr_result (SubcircuitRecognitionResult)
fbr_result (FunctionalBlockRecognitionResult)
topology (TopologyTemplate)
tech (TechParams)
spec (SizingSpec)
time_limit_s (float)
- Return type: